This invention relates to integrated circuits, and more particularly, to ways in which to improve circuit performance by compensating for the effects of metal-oxide-semiconductor (MOS) transistor threshold voltage drift and temperature changes.
Integrated circuits based on complementary metal-oxide-semiconductor (CMOS) transistor technology are widely used in modern electronic systems. The proper performance of CMOS integrated circuits is often critically dependent on the stable operation of its MOS transistors. Even relatively small changes in transistor performance can have a strong impact on the operation of sensitive circuitry on a high-performance CMOS chip.
The operation of a transistor can be significantly affected by variations in temperature and changes in the transistor's threshold voltage due to aging. If a transistor's threshold voltage increases even slightly, the transistor's ability to drive current may be reduced sufficiently that a sensitive digital logic circuit in which the transistor is operating will slow down substantially or no longer function properly and the gain of certain sensitive analog circuits may be degraded. This can disrupt the proper functioning of the entire integrated circuit.
CMOS integrated circuits contain p-channel (PMOS) and n-channel (NMOS) transistors. The threshold voltage of a PMOS transistor can change over time due to negative bias temperature instability (NBTI). Negative bias temperature instability arises when MOS devices are exposed to low gate bias voltages under elevated operating temperatures. Threshold voltage increases due to NBTI may be significant—i.e., on the order of tens of millivolts over the lifetime of a circuit. The threshold voltages in NMOS transistors may also increase over time due to the accumulation of gate-oxide charge from hot carrier effects.
It is an object of the present invention to provide ways in which to overcome variations in transistor performance due to changes in operating temperature and shifts in threshold voltages.